Performance enhancement between generations of conventional CMOS integrated circuit is generally achieved by applying shorter gate length and thinner gate oxide in MOS transistors fabricated on bulk or silicon-on-oxide (SOI) wafers. This is generally referred to as the “scaling” of MOS transistors.
Metal-Oxide-Semiconductor-Field-Effect-transistors (MOSFETs), having a source, a drain region, and a gate electrode formed using a gate oxide, are commonly used in IC devices. As the gate oxide becomes thinner, the transistors be powered with a lower voltage to avoid breakdowns and leakage through the gate-oxide.
Additionally, as CMOS transistors on bulk silicon are scaled to channel lengths below 100 nm, conventional CMOS transistors suffer from degraded performance as resulting from leakage currents that occur through channels, junctions, and gate dielectrics. In particular, interactions between the source and drain of the CMOS device, typically results in both Vt roll-off and poor sub-threshold swing, degrade the ability of the gate to control whether the transistors is on or off. This phenomenon is typically referred to as the “short-channel effect”.
To overcome the degraded performance of CMOS fabricated on bulk silicon, CMOS transistors fabricated on SOI structure may be used.
In the generation of layouts, a MOSFET transistor can typically be defined by a silicon active area that-intersects with one or more polysilicon lines. The silicon active area is often a two-dimensional, planar layer of silicon.
MOSFETs fabricated on SOI are formed with an insulator (usually, silicon dioxide, and referred to as buried-oxide or “BOX”) below the device active region, unlike conventional “bulk” MOSFETs, which are formed directly on silicon substrates, and hence, have silicon below the active region. The use of SOI MOSFETs increases device speed over that of CMOS on bulk through smaller sub-threshold voltage swings (i.e. better switching off performance). Additionally, there is reduced coupling between the source and the drain of the MOSFET on SOI as blocked by the “BOX” layer below the channel as well as the source and drain. As device size is scaled, however, this becomes increasingly difficult, since the distance between the source and drain is reduced, and hence, both the source and the drain increasingly interact with the channel, thus reducing gate control and increasing short channel effects (SCE).
As shown in prior art FIGS. 1-2, a FinFET on SOI structure 10 has a thin channel or “fin” region disposed on a SOI. The fin 12 is a silicon shape built on Silicon On Insulator (SOI) with “BOX” 16 and silicon substrate 14, and extends vertically out of the plane of the substrate. The vertical sides of the fin (together with the top planar portion) can be utilized to form the channel of FETs. These FETs incorporated into fin structures are referred to as FinFETs (also commonly referred to as double-gate FinFET or tri-gate transistor in literature). Several embodiments of FinFET transistors on SOI wafer are disclosed in detail in Hu, U.S. Pat. No. 6,413,802 B1, issued on Jul. 2, 2002, which is herein incorporated by referenced.
The FinFET structure on SOI 10 has at least one thin vertical fin 12 and self-aligned gates 18 “wrapped around” or over both sides and the top of the at least one thin vertical fin 12. The thin vertical fin can result in the well-known “thin-body” effects, e.g. enhanced mobility and volume inversion. The “wrap around gate” 18 places a gate so that it completely or almost-completely surrounds the fin 12 or channel and thus, provides excellent gate control for turn-off and turn-on performance with the known advantages of “thin-body” effects. The SCE is also improved due to the elimination of electrostatic coupling between the source and drain by the buried oxide (BOX) layer 16 disposed beneath the device active area.
Preferably, a wider channel transistor 19 may be formed by multiple fins 21 in parallel with a common gate 23 as shown in FIG. 3.
Both the CMOS and FinFET on SOI of prior art FIGS. 1, 2a-f, and 3 have demonstrated superior performance over planar CMOS on bulk silicon in suppression of short-channel effects and reducing leakage currents.
The fabrication of prior art FinFET on SOI structure is in a similar manner to that of planar CMOS on bulk silicon. Prior art FIG. 1 is an illustration of a FinFET transistor on SOI having one silicon fin. The fin 12 has a thickness (or width) of about 10 nm and can be formed using existing technology such as e-beam lithography.
Typically, the width, or thickness of each silicon fin ranges between 10 to 40 nm. Additionally, the height of the fin ranges between 30 to 100 nm. The height-to-width ratio or “aspect ratio” of the fin, approximately in the range of 1 to 3, is higher than that of a planar CMOS fabrication process.
In general, all of the thin fins have the same height and thickness (or width). Wide transistors can be formed by providing parallel multi-fins that share a common gate (see FIG. 3).
As shown in FIGS. 2a-f, the fabrication of FinFET on SOI is similar to that of conventional planar CMOS fabricated on bulk silicon as is well known by a person of ordinary skill in the art.
Prior art FIGS. 2a-f illustrate the process of fabricating a FinFET on SOI structure.
FIG. 2a shows Fin formation by patterning, etching, and Vt implanting. The silicon fins (un-doped) 12 are formed first by fine lithography (e.g. e-beam) and then followed by silicon etching and an optional Vt implant 24. As shown in FIG. 2a, the Vt implantation after silicon etching is optional for adjustment of Vt depending on which gate conduction materials are used.
Unlike the fabrication of CMOS on bulk substrate, a formation of shallow trench isolation (STI) is not necessary because the buried oxide layer of SOI provides good isolation.
As shown in FIG. 2b, after the fin patterning process is performed, the surface of the fin 12 is oxidized to form a gate oxide (GOX). Next, after gate oxidation, a gate conductor film, preferably selected from at least one of poly-Si, Mo, and TiN, is deposited over the silicon fin and is patterned as the gate conductor 18. Preferably, the gate is patterned by an etching process to form perfectly aligned gates straddling over the two sidewalls of the patterned fin. The resulting channel width is calculated to be about 2 times the fin-height associated with each fin, wherein the fin-height is the thickness of the silicon layer of the FinFET on SOI structure.
The threshold voltage, Vt, of the device can be controlled by adjusting the work function of the gate conduction material using a refractory metal, a compound such as titanium nitride, or an alloy such as silicon-germanium alloy. The Vt is determined as well-known in the art by the work function of the gate conduction material and a density value of carriers in the silicon fin at an on-state.
FIG. 2c illustrates a selective implantation of a lightly doped drain (“LDD”) region using a large tilt angle implant 28 into the selective surface of the substrate, thus providing uniformity. The arrows in different angles in FIG. 2c schematically represent the “large angle tilting” during implanting. The photo resist 20 pattern is formed by a typical masking step. The selective LDD implant is therefore performed for n-channel and p-channel regions respectively.
As shown in FIG. 2d, a spacer 30 is formed on the sidewall of the gate 18 and the fin (not underneath the gate) by deposition and a chemical removal process (eg. etch-back technique). The spacer material is typically silicone dioxide or silicon nitride.
After the spacer is formed, the silicon portion of the fin is exposed (i.e. the portion not underneath the gate and the spacer) to form the source and the drain by heavy N+ or P+ implant using masking steps (not shown in FIG. 2d).
As shown in FIG. 2e, a thin layer of silicide 32 is performed using the well-known self-aligned silicide technology. The process of silicides consumes a small amount of silicon at the source and the drain area. Possible silicides include nickel silicide or palladium silicide, and are not limited to commonly used silicides, e.g. titanium silicide and cobalt silicide.
Alternatively, another selective conductor deposition process such as selective metal, polysilicon, or epitaxial silicon deposition may be performed as shown in FIG. 2e to replace the silicide layer 32.
SOI technology further improves the speed and reduces the operating power of the circuits. The BOX layer not only reduces the capacitance of the source and the drain junction so it operates faster, but also eliminates the coupling between the source and the drain, which degrades transistor performance (i.e. short channel effects in Vt roll-off, sub-threshold swing, and higher leakage current) in the case of CMOS on bulk technology.
The FinFET on SOI technology is generally superior to planar CMOS, however, the FinFET on SOI device has a quasi-planar surface that imposes significant challenges in processing including: providing a suitable SOI substrate, performing fine lithography, performing etching with a high aspect ratio, using a large tilt angle implant to produce a uniformly doped source and drain, and LDD regions. The source and drain regions are actually located “above” the lowest channel region of the FinFET, thus, the source and drain regions of FinFET are the “raised source and drain” with known advantages of reducing coupling between the source and drain through the channel region.
Additionally, FinFET as any MOS transistors fabricated on SOI wafers suffer from a “floating body effect”. The floating body effect occurs as a result of the floating channel region, where it can be electrically charged to various voltage levels during switching on and off. This floating body effect leads to a less reproducible behavior of the transistors. MOS transistors fabricated on bulk have no “floating body effects”, since the channel region is electrically connected to the substrate.
Therefore, it is an object of the present invention to overcome the disadvantages of both planar CMOS and FinFET on SOI technology.